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ADSL Analog Front End AFE1302 Datasheet for Fiber Optic Devices
The AFE1302 consists of a transmit (TX) channel, a receive (RX) channel, a digital interface to connect to an ADSL DSP, and VCXO circuitry and a VCXO control DAC are included for precise clock generation. The AFE1302 is designed to be used with external amplifiers and filters for noise reduction and dynamic range improvement.
According to the description from its original manufacture site, Texas Instruments, this device can reduce the size and cost of an ADSL-compliant system by providing the active analog circuitry needed to connect an ADSL Digital Signal Processor (DSP) to an external line driver, receiver, TX/RX filters, hybrid, transformer, and POTS filter.
The TX channel receives digital data at the nominal rate of 1.104MWords/s to 8.832MWords/s and are interpolated up to the AFE1302 clock rate of 35.328MHz. In the RX channel, the analog receive signal is input to a PGA. The output of the first-order, switched capacitor filter is digitized with a 16-bit delta-sigma ADC, that’s why it ensures decimation filter for compliant word rate 1.104MWords/s to 8.832MWords/s to the ADSL digital chip.
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